A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

A current generation circuit includes a metal-oxide-semiconductor (MOS) transistor having a source terminal coupled to one line of a power supply line and a ground line, a voltage generation circuit configured to generate a first voltage corresponding to a resistance value of wiring between the one line and the source terminal, and a control circuit configured to cause the MOS transistor to generate a predetermined current based on the first voltage.

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

An air conditioning controller for controlling an air conditioner by an operation of an operator. The air conditioning controller is convenience to the operator to carry. The air conditioning controller includes a controller unit having an operating part by which the operator operates the air conditioner, a holder holding the controller unit at a predetermined position, and an electrical switch for switching an electrical power supply line between a first position that the controller unit positions outside of the holder and that the electric power from an internal battery is supplied to a controlling part of the controller unit and a second position that the controller unit positions in the holder and that the electric power from an electrical power source is supplied to the controlling part of the controller unit.

A driving circuit includes a first reference terminal, a second reference terminal, at least one input terminal, an output terminal, a first transistor, a second transistor, a switch module, and at least one control signal terminal. The at least one input terminal receives at least one input signal. The output terminal outputs an output signal in response to the at least one input signal. The first transistor and the second transistor respectively include control terminals coupled to the at least one input terminal. The switch module includes at least one control terminal coupled to the at least one control signal terminal to receive at least one control signal. The at least one input signal has a transition period. The switch module can be turned off according to the at least one control signal.

A driving apparatus for driving a switching device is provided, the driving apparatus including: a high potential line; a high-potential-side switching control unit configured to perform switching as to whether to connect a control terminal of the switching device to the high potential line; a first resistor element located on a high-potential side and disposed in series with the high-potential-side switching control unit on a path from the control terminal of the switching device to the high potential line; a high-potential-side capacitor provided in parallel with the first resistor element on the path from the control terminal of the switching device to the high potential line; and a high-potential-side discharge control unit configured to control whether to discharge the high-potential-side capacitor.

A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.

A driver circuit includes a high side transistor, a low side transistor, a first trigger circuit, and a second trigger circuit. The high side transistor has a first control terminal and a first current path coupled between a first voltage terminal and an output voltage terminal. The low side transistor has a second control terminal and a second current path coupled between the output voltage terminal and ground. The first trigger circuit is coupled to the first control terminal, the first voltage terminal, and the output voltage terminal. The first trigger circuit is operable to protect the high side transistor. The second trigger circuit is coupled to the second control terminal, the first trigger circuit, and ground. The second trigger circuit is operable to protect the low side transistor.