An output driver is provided. The output driver includes: a pull-up driver connected between an output power supply voltage and an output node, and configured to pull up a voltage at the output node based on a pull-up driving signal and a pull-up reference voltage; a pull-down driver connected between the output node and a ground voltage, and configured to pull down the voltage at the output node based on a pull-down driving signal and a pull-down reference voltage; and a reference voltage compensation circuit configured to perform a short operation during transitions of the pull-up driving signal and the pull-down driving signal, wherein the short operation includes electrically connecting any one or any combination of the pull-up reference voltage to the ground voltage, and the pull-down reference voltage to the output power supply voltage.

This application discloses a communication circuit, a control method, and an electronic device. The circuit includes a plurality of optical image stabilizers OIS, a gyroscope, and a control circuit, where an input terminal of the control circuit is connected to a power terminal, an output terminal of the control circuit is connected to the plurality of OISs separately, and the plurality of OISs are all connected to the gyroscope; and the control circuit controls one of the plurality of OISs to conductively connect to the gyroscope and establish a communication connection.

A ring-oscillator control circuit (100) including voltage reference (110), a ring oscillator (120), a power supply (130, 140) and a supply controller (150). The supply controller (150) is configured to select the power supply (130, 140) among an energy storage (130) and an energy source (140) such as to supply the ring oscillator (120) in function of the voltage reference (110).

The present disclosure relates to a power supply device for a protective relay. The power supply device comprises a power circuit for supplying a power to the control circuit, wherein the power circuit includes: a semiconductor switch element having an input terminal connected to a first node for receiving a direct current, and an output terminal connected to a reference node, wherein the reference node has a voltage lower than a voltage of the first node; and a first voltage drop element disposed between the first node and a second node, wherein the second node is connected to a switching terminal of the semiconductor switch element.

An aspect relates to an apparatus including a first pair of switching devices configured to selectively couple an application processor to a Universal Serial Bus (USB) differential data transmission lines; a USB host port connector coupled to the USB differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively.

A circuit includes a solid-state relay, a rectifier, and a current transformer-based power supply. The rectifier is adapted to be coupled to the solid-state relay. The rectifier is configured to provide a voltage to an output terminal responsive to the solid-state relay being in an off state. The current transformer-based power supply is coupled to the rectifier and is adapted to be coupled to a transformer. The current transformer-based power supply is configured to provide a voltage to the output terminal responsive to the solid-state relay being in an on state.

A controller protection circuit for a voltage power optimiser. The circuit having: a first terminal for connecting to a first end of a winding in the voltage power optimiser; a second terminal for connecting to a second end of the winding in the voltage power optimiser; and a thyristor. The controller protection circuit also includes a thyristor gate control circuit. The thyristor gate control circuit is configured to: set the gate control signal such that the thyristor is configured to conduct in response to a potential difference between the anode terminal and the cathode terminal of the thyristor; and set the gate control signal such that the thyristor is configured not to conduct in response to a signal received from a voltage controller. The thyristor gate control circuit includes a normally-on switch having a conduction channel and a control terminal, and a photovoltaic isolator configured to set the gate control signal such that the thyristor is configured not to conduct in response to a signal received from a voltage controller.

A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.