An input stage for an LVDS receiver circuit is provided, which includes at least one supply voltage connection as well as a first and a second stage input to be acted upon by a differential input signal pair. The input stage further includes a first and a second differential stage, the stage inputs being directly connected to one input each of the first differential stage and indirectly, via one level-shifting circuit each, to one input each of the second differential stage. According to the present invention, the first and the second differential stage are connected to the supply voltage connection via one transistor each of a third differential stage, the control input of one of these transistors being connected to a measuring path connecting the stage inputs to one another, with the control input of the other transistor being connected to an apparatus/device (arrangement) for providing a reference voltage.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.

A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.

A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.

A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.

A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.