Aspects of the subject disclosure may include, for example, N-to-1 multiplexers and pulse generators that include NOR logic. The NOR logic pulse generators may include parallel transistors responsive to data and clock signals to pull down an output node when any of the data or clock signals are asserted. The NOR logic pulse generator may also include a pullup structure that includes no more than one active device channel in series between a supply node and the output node. Other embodiments are disclosed.

A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.

The invention provides a scan driving circuit for an oxide semiconductor thin film transistor and a NAND logic operation circuit thereof. The NAND logic operation circuit includes: a first inverter and a second inverter applied to a pull-down holding circuit of a GOA circuit, and multiple transistors. The invention uses the combination of NFTF and inverter to replace a function of original PMOS elements and thereby achieves characteristics similar to that of the original CMOS NAND operation circuit. Accordingly, the invention can solve the design problem of IGZO TFT single type of device logic operation circuit and thus is more suitable for integrating a large scale digital integrated circuit on a liquid crystal display device.

In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.

An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

An IC device includes a transistor including a first gate structure extending in a first direction, first and second source/drain (S/D) structures adjacent to the first gate structure in a second direction perpendicular to the first direction and extending across a first elevation in a third direction perpendicular to each of the first and second directions and first and second S/D metal portions overlying the respective first and second S/D structures and extending across a second elevation in the third direction, a dielectric layer extending across the first elevation, a third S/D metal portion including a same conductive material composition as that of the first and second S/D metal portions, overlying the dielectric layer, and extending across the second elevation, first and second vias overlying the dielectric layer, and a third via overlying the first S/D metal portion and electrically connected to the first via.

A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.