Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

The present invention is directed to methods and compositions for generating a pool of oligonucleotides. The invention finds use in preparing a population or subpopulations of oligonucleotides in solution. The pool of oligonucleotides finds use in a variety of nucleic acid detection and/or amplification assays.