A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.

In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.

Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.

In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.

An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.