An apparatus for network switching may include a plurality of input ports, a plurality of output ports, and a subset of pre-configured interconnection patterns including some but not all of the possible interconnection patterns between the input ports and the output ports. The apparatus may be communicatively coupled to a network via the input ports and/or the output ports. The apparatus may be configured to switch to a first interconnection pattern and a second interconnection pattern from the subset of pre-configured interconnection patterns. The first interconnection pattern and the second interconnection pattern may each provide a set of connections between the input ports and the output ports. At least one signal between the input ports and the output ports may be transmitted via the first interconnection pattern and/or the second interconnection pattern. Related methods are also provided.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

Embedded antennas in integrated circuits, and methods of making and using the same, are provided herein. An integrated circuit within a semiconductor die may include a control circuit; an antenna configured to wirelessly receive a control signal at a predefined frequency; and an interconnect configured to provide the received control signal from the antenna to the control circuit. The control circuit may be configured to control a function of the integrated circuit responsive to the received control signal.

An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

A timer circuit switches a second changeover switch and a third changeover switch to a pulse output unit for a certain period of time when power supply is started, and causes the pulse output unit to output a code pulse to a second communication line. An input-output control unit switches a first changeover switch to a first terminal for the certain period of time when the power supply is started, determines whether a code indicated by the code pulse received from the first terminal is a regular code, and cuts off electric power supplied from a first power supply line to a second power supply line when the code is not the regular code.

A field programmable gate array (FPGA) comprises a set of configurable logic blocks (CLBs), input/output blocks (IOBs), and interconnect wiring for communicating data between the CLBs and IOBs. A resonating circuit provides a resonating signal to the circuit blocks. The circuit blocks provide the resonating signal to the interconnect wires to communicate a first binary value, and a static voltage to communicate a second binary value. The output signals of the circuit blocks change state when the resonating signal is at or near the static voltage. This reduces switching losses that exist within prior art FPGAs.

A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.

The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

A communications system includes: a control device; a standard proxy input/output circuit configured to control a standard electric device; and an extension proxy input/output circuit configured to control an extension electric device. The control device and the standard proxy input/output circuit are provided on one substrate, and the control device and the extension proxy input/output circuit are connected to each other via an electric wire.