The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit.

Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.

Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.

A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.

A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding sub array of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

An analog hashing system and method includes: an input port for accepting an input signal; a chaotic circuit including non-linear components and multiple chaotic attractors for generating an unpredictable output responsive to the input signal; a differential output port coupled to the chaotic circuit for producing an analog differential signal from the unpredictable output; and a clock circuit for producing a binary output, as a hash function, generated by the sign of the analog output in every clock cycle.

A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a M.sub.x layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the M.sub.x layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a M.sub.y layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the M.sub.y layer that is coupled to the second output on the fifth track.