An FPGA can be started up without system failure when a soft error occurs. A configuration control system includes: a first semiconductor chip which is capable of programming a logic circuit inside an LSI; a semiconductor memory which stores a plurality of pieces of circuit information of the first semiconductor chip; and a second semiconductor chip which, when controlling a configuration of the semiconductor chip using the circuit information stored in the semiconductor memory, if the configuration using any one of the plurality of pieces of circuit information fails, performs a re-configuration using another piece of circuit information among the plurality of pieces of circuit information.

Systems and methods for time-multiplexed synchronous logic provide an enhanced time delay multiplexing (TDM) scheme that includes soft TDM logic generated by computer-aided design (CAD) tools to actualize a circuit design with improved density. The CAD tools can be used to utilize inherent regularity to devise time multiplexing user logic. The CAD can generate soft TDM hardware to realize a circuit design with improved density.

An FPGA can be started up without system failure when a soft error occurs. A configuration control system includes: a first semiconductor chip which is capable of programming a logic circuit inside an LSI; a semiconductor memory which stores a plurality of pieces of circuit information of the first semiconductor chip; and a second semiconductor chip which, when controlling a configuration of the semiconductor chip using the circuit information stored in the semiconductor memory, if the configuration using any one of the plurality of pieces of circuit information fails, performs a re-configuration using another piece of circuit information among the plurality of pieces of circuit information.

Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.

A method for upgrading a programmable logic device (PLD) in a network element is provided. The method includes writing PLD configuration data to a nonvolatile memory and directing a signal control device external to the PLD to hold system control signals in the network element at a predefined state irrespective of direction by the PLD. The method includes loading the PLD configuration data from the nonvolatile memory into a PLD configuration memory in the PLD, while the signal control device holds the system control signals at the predefined values. The method includes directing the signal control device to release the holding the system control signals, so that the PLD directs the system control signals, responsive to completion of the loading the PLD configuration data into the PLD configuration memory. A network element is also provided.

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals.

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals.

Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals.

A reconfigurable device-based programmable wiring system includes switches. A total number of switches is based on a total number of peripheral terminals and a total number of microcontroller pins. The total number of switches is based on a product of a total number of peripheral terminals and a total number of microcontroller pins. The reconfigurable device-based programmable wiring system includes multiple microcontroller peripherals.