Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.

A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A field programmable gate array (FPGA) comprises a set of configurable logic blocks (CLBs), input/output blocks (IOBs), and interconnect wiring for communicating data between the CLBs and IOBs. A resonating circuit provides a resonating signal to the circuit blocks. The circuit blocks provide the resonating signal to the interconnect wires to communicate a first binary value, and a static voltage to communicate a second binary value. The output signals of the circuit blocks change state when the resonating signal is at or near the static voltage. This reduces switching losses that exist within prior art FPGAs.

A field programmable gate array (FPGA) comprises a set of configurable logic blocks (CLBs), input/output blocks (IOBs), and interconnect wiring for communicating data between the CLBs and IOBs. A resonating circuit provides a resonating signal to the circuit blocks. The circuit blocks provide the resonating signal to the interconnect wires to communicate a first binary value, and a static voltage to communicate a second binary value. The output signals of the circuit blocks change state when the resonating signal is at or near the static voltage. This reduces switching losses that exist within prior art FPGAs.

A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.