A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.

According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

Examples described herein provide for attestation of memory dies using a respective memory identifier of the memory die itself. A memory device may include a memory die with a memory array, attestation logic, and programmable circuitry that stores a memory identifier associated with the memory array. The attestation logic may generate an encryption key pair based on the memory identifier stored in the programmable circuitry. Advantageously, by attesting memory die using a memory identifier stored in programmable circuitry, examples of systems and methods described herein may provide increased security for data processed by memory die. For example, a non-attested or compromised memory die may be remediated. The attestation of memory dies may include attestation of memory dies on wireless devices, drones, vehicles, and/or Internet-of-Things devices.

Examples described herein provide for attestation of memory dies using a respective memory identifier of the memory die itself. A memory device may include a memory die with a memory array, attestation logic, and programmable circuitry that stores a memory identifier associated with the memory array. The attestation logic may generate an encryption key pair based on the memory identifier stored in the programmable circuitry. Advantageously, by attesting memory die using a memory identifier stored in programmable circuitry, examples of systems and methods described herein may provide increased security for data processed by memory die. For example, a non-attested or compromised memory die may be remediated. The attestation of memory dies may include attestation of memory dies on wireless devices, drones, vehicles, and/or Internet-of-Things devices.

A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Various embodiments provide apparatuses, systems, and methods for a hot carrier injection (HCI) physically unclonable function (PUF) circuit. For example, described herein is a HCI PUF circuit with n-type metal oxide semiconductor (NMOS) transistors and a Pi-shaped reset structure. Other embodiments may be described and claimed.

A physical unclonable function (PUF)-based method for enhancing system reliability is provided, including: requesting, by a client, data transmission with a server; randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices; calculating, by the server, a probabilistic PUF that the trap in each of the plurality of MOS devices is occupied by a carrier and constructing a probabilistic model; randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; and determining, by the server, an occupancy probability of the trap in each of the plurality of MOS devices at the detection time according to the probabilistic model, and generating a theoretical code key.

A physical unclonable function (PUF)-based method for enhancing system reliability is provided, including: requesting, by a client, data transmission with a server; randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices; calculating, by the server, a probabilistic PUF that the trap in each of the plurality of MOS devices is occupied by a carrier and constructing a probabilistic model; randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; and determining, by the server, an occupancy probability of the trap in each of the plurality of MOS devices at the detection time according to the probabilistic model, and generating a theoretical code key.

The present disclosure provides a PUF circuit including a first array including at least one physically unclonable function (PUF) cell, a second array including at least one PUF cell, and a controller which selects a first PUF cell from the first array and selects a second PUF cell from the second array and generates unique information represented by the first PUF cell and the second PUF cell based on a first output voltage output by the first PUF cell and a second output voltage output by the second PUF cell.