An analog circuit has a first plurality of transistors that are connected as a first selectable resistance in the analog circuit, and a second plurality of transistors that are connected as a second selectable resistance in the analog circuit. In an unlocked state of the analog circuit, the first selectable resistance matches the second selectable resistance within a designed ratio and tolerance. In a locked state of the analog circuit, the first selectable resistance and the second selectable resistance do not match within the designed ratio and tolerance. A controller retrieves a logic lock key from an off-chip memory and selects the first and second selectable resistances, thereby setting the analog circuit to its unlocked state, by sending respective first and second portions of the logic lock key to operate the first and second pluralities of transistors.

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.

A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.

In this paper, a novel field-programmable analog array (FPAA) is proposed to secure the intellectual property (IP) of analog and mixed-signal circuits. A obfuscation technique is developed to efficiently mask the topology of both differential mode and single-ended mode analog circuits.

In this paper, a novel field-programmable analog array (FPAA) is proposed to secure the intellectual property (IP) of analog and mixed-signal circuits. A obfuscation technique is developed to efficiently mask the topology of both differential mode and single-ended mode analog circuits.

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a φ-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the φ-bit protected Obfuscation Key generated by the LFSR, and output k└φ×α┘-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.