A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

A physical unclonable function (PUF)-based method for enhancing system reliability is provided, including: requesting, by a client, data transmission with a server; randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices; calculating, by the server, a probabilistic PUF that the trap in each of the plurality of MOS devices is occupied by a carrier and constructing a probabilistic model; randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; and determining, by the server, an occupancy probability of the trap in each of the plurality of MOS devices at the detection time according to the probabilistic model, and generating a theoretical code key.

A physical unclonable function (PUF)-based method for enhancing system reliability is provided, including: requesting, by a client, data transmission with a server; randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices; calculating, by the server, a probabilistic PUF that the trap in each of the plurality of MOS devices is occupied by a carrier and constructing a probabilistic model; randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; and determining, by the server, an occupancy probability of the trap in each of the plurality of MOS devices at the detection time according to the probabilistic model, and generating a theoretical code key.

Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.

Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.