A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.

An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule.

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

A semiconductor in which the area of a circuit that is unnecessary during normal operation is small is provided. A semiconductor device including a first circuit has a function of storing a start-up routine in the first circuit and executing the start-up routine, a function of operating the first circuit as a buffer memory device after executing the start-up routine, and a function of loading the start-up routine into the first circuit from outside before the semiconductor device is powered off.

The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.

In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.

A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.