A DLL circuit comprising a delay circuit, a phase detector and a counting control circuit. The delay circuit is configured to receive a reference clock signal, and delay the reference clock signal to output a delayed clock signal. The phase detector is configured to detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal. The counting control circuit is configured to generate a control delay signal according to the phase difference signal. The delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal. When the counting control circuit is in the first mode, the counting control circuit has a first update frequency. When the counting control circuit is in the second mode, the counting control circuit has a second update frequency.

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to N.sup.th data, where N is an even number equal to or greater than 2, and first to N.sup.th multi-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to N.sup.th data that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to N.sup.th multi-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.

A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.

Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.