Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.

A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.

A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109) with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner (130) is configured to provide the digitally represented output signal (139) based on the digitally represented constituent output signals (131, 132, 133) of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.

Disclosed is a tuner device including an input terminal, a separator, a first amplifier, a second amplifier, and a tuner. The input terminal receives an input of a reception signal of satellite digital broadcasts. The separator is connected to the input terminal and adapted to frequency-separate a first signal and a second signal. The first signal is in a low-frequency domain of the reception signal, and the second signal is in a high-frequency domain of the reception signal. The first and second amplifiers respectively amplify the first and second signals. The tuner receives an input of output signals from the first and second amplifiers.

A delay circuit includes a coarse delay circuit, a header circuit, and a phase mixing circuit. The coarse delay circuit is configured to delay a reference clock signal to generate a first clock signal and a second clock signal and to change each phase of the first clock signal and the second clock signal by double a unit phase. The header circuit is configured to receive the first clock signal and the second clock signal and to generate a first phase clock signal and a second phase clock signal, between which a phase difference corresponds to half of the unit phase. The phase mixing circuit is configured to mix phases of the first phase clock signal and the second phase clock signal to generate an output clock signal.

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.