A frequency generator for generating a controlled signal having a controlled frequency uses a frequency ratio generator with an input; a frequency divider for dividing the controlled frequency by a frequency ratio signal to generate a divided signal having a divided frequency; a converter for generating an excitation signal having the divided frequency, the excitation signal exciting a resonator for generating a resonance signal having a resonance frequency; a frequency phase detector of a phase difference between the divided frequency and the resonance frequency; an inner loop filter for generating the frequency ratio signal and filtering the phase difference signal to prevent instability of two frequency ratio generator loops; an output configured for providing the frequency ratio signal based on a ratio between the controlled frequency and the resonance frequency; and a controlled oscillator circuit for generating the controlled signal based on comparison of the frequency ratio with a target ratio.

An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

Disclosed is a phase-locked loop circuit, including: a phase-locked loop, a locking detection circuit, an input end for inputting a reference clock signal, a first output end for outputting an oscillator clock signal, and a second output end for outputting a locking signal, wherein the phase-locked loop is configured to output the oscillator clock signal according to the reference clock signal and control the reference clock signal and the oscillator clock signal to be synchronous; and the locking detection circuit is configured to output the locking signal to the second output end when the oscillator clock signal and the reference clock signal are synchronous.

In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.