A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.

A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a counter whose output sequence changes only one bit per counted controlled oscillator output cycle, such as a Gray counter. It further includes a register or latches, which sample(s) the counter output value upon receiving a reference clock pulse. The latches output value represents the measured phase. A binary encoder, such as a Gray-to-binary converter, may translate the measured phase to a binary number. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.