A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Disclosed is a tuner device including an input terminal, a separator, a first amplifier, a second amplifier, and a tuner. The input terminal receives an input of a reception signal of satellite digital broadcasts. The separator is connected to the input terminal and adapted to frequency-separate a first signal and a second signal. The first signal is in a low-frequency domain of the reception signal, and the second signal is in a high-frequency domain of the reception signal. The first and second amplifiers respectively amplify the first and second signals. The tuner receives an input of output signals from the first and second amplifiers.

The present disclosure relates to a circuit and method of operation thereof for linearized time amplifier architecture for sub-picosecond resolution. More particularly, the disclosure is directed to an asymmetric edge manipulator whose output is fed to four series of transistors and is operatively coupled to a reset. The disclosure relates to outputting a pair of signals that correspond to a first input and second input of a known and measured clock that may be adjustable with gain to be perceptible to an external device that can then correct for the gain to allow measurement of sub-picosecond resolution.

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.

A method for a radar device is described. According to one example implementation, the method comprises generating an RF signal using a voltage-controlled oscillator (VCO), wherein the frequency of the RF signal depends on a first tuning voltage and a second tuning voltage. The method also comprises setting the second tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency. The first tuning voltage is changed in such a manner that the second tuning voltage set by the phase-locked loop corresponds approximately to a predefined value. Another example implementation relates to a method for a radar device comprising: generating an RF signal using a VCO, wherein the frequency of the RF signal depends on a tuning voltage, setting the tuning voltage using a phase-locked loop coupled to the VCO, with the result that the frequency of the RF signal corresponds to a desired frequency, and determining a differential VCO gain of the VCO. The bandwidth of the phase-locked loop is set on the basis of the determined VCO gain.

A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.

A frequency-agile phase modulator with glitch-free multiplexer in CMOS process technologies for applications including wireless communications, radar, automotive radar, etc. Examples herein offer a novel phase modulator architecture that, when combined with either a wideband power amplifier or multiple narrowband amplifiers, allows for a single transmitter to transmit radar, communication, telemetry, or other similar waveforms across multiple frequency bands. The embodiments herein allow one transmitter to cover a very large operating frequency range, resulting in a decrease in size, weight, power consumption, and cost for future small platform systems. In an embodiment, the phase modulator circuit includes a reconfigurable delay-locked loop (DLL) circuit that is configured to receive a radio frequency (RF) input signal (RF.sub.in) and a configuration signal. The phase modulator circuit also includes a frequency-agile, glitch-free multiplexer circuit configured to receive an oversampled baseband clock signal (clk.sub.OBB) and a phase select data input signal.

A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.