A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

A delay line includes first to n-th delay cells and a dummy delay cell, n being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to nth output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding to delay cell, and a delay amount of the nth delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

The present disclosure includes a frequency divider circuit that includes a superharmonically injection-locked ring oscillator, injection circuitry, and various switches. The input can include a collection of signal components at different phases that are all at the same, but changeable, frequency. The divider's division ratio can be changed during the divider's operation by, for example, utilizing one or more switches to change: the number of stages in the ring oscillator, and/or which stage(s) of the ring oscillator are injected into by which input signal components.

A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.

Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.