A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

A phase-locked loop of the disclosure includes a detector, an oscillator, an adjuster, and a controller. The detector detects a transition of an input clock signal. The oscillator generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector. The adjuster adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal. The controller compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.

A circuit includes a ring oscillator and a state capture register to receive a multi-bit state of the ring oscillator captured upon occurrence of an edge of input periodic signal. The circuit also includes an edge-phase detector to assert an edge detect high signal in response to a first reference clock derived from the ring oscillator being high upon occurrence of the edge of the input periodic signal and to assert an edge detect low signal in response to the first reference clock derived from the ring oscillator being low upon occurrence of the edge of the input periodic signal. A first register receives data from the state capture register upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator.

A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.