A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors

An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.

Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.