A PLL circuit includes a phase comparator, first and second charge pumps, a filter generating a first control voltage from a current of the first charge pump, a comparator comparing a voltage of a first node with a reference voltage, a switch section outputting the reference voltage to the first node and outputting a current of the second charge pump to a second node in a high-speed lock mode, and outputting the current of the second charge pump to the first node and outputting a result from the comparator to the second node in a normal lock mode, a second filter generating a second control voltage by integrating a current of the first node, a third filter generating a third control voltage by integrating a current of the second node, and a voltage controlled oscillator generating a clock signal of a frequency corresponding to the first to third control voltages.

The present invention relates to a voltage controlled oscillator and phase locked loop comprising the same for compensating a noise of a power voltage. According to an embodiment of the present invention, a voltage controlled oscillator may comprise: an oscillator comprising a plurality of inverters connected as a ring form for generating a plurality of signals having different phases with each other, and a plurality of feed forward circuits formed between the inverters; and a controller for controlling the inverter and feed forward circuit based on a detected noise by detecting a noise of a power voltage.

A tunable fractional phase locked loop (PLL) (hereinafter tunable PLL) is described herein and includes a controller configured to tune the tunable PLL to a range of frequencies corresponding to a frequency of the input clock signal. The tunable PLL includes a phase detector configured to receive an input clock signal and a feedback signal, a voltage controller oscillator (VCO) configured to receive the error signal from said phase detector and in response thereto to generate a VCO clock signal, a controller configured to generate a dithered division ratio having an average value corresponding to a ratio of a number of edges of the VCO clock signal generated in a cycle of the input clock signal, and a feedback module configured to generates a feedback signal to tune the PLL such that the PLL operates in the range of input frequencies of the input clock signal.

It was found that certain VCO devices used in microwave frequency synthesizers exhibit prolonged ringing oscillation during extreme voltage jumps above a critical limit, but that this effect could be significantly reduced by splitting the voltage adjustment over multiple steps. This finding was used to improve the switching speed of such devices (e.g. wideband VCO with a computer processor, base frequency generator VCO and a frequency divider). Here, before implementing a command to switch frequencies (by changing the base frequency oscillator and frequency divider settings), the processor first determines if this change will require an extreme voltage jump likely to cause such oscillations. If so, the processor implements this voltage jump as a multiple step process, resulting in a significant reduction in the maximum time required to switch frequencies.

The present disclosure relates to oscillating circuitry, comprising a controllable oscillator operable to generate an output signal having an output frequency dependent on a coarse value and a fine value, the coarse value causing the output frequency to be within an associated band of output frequencies and the fine value controlling the output frequency within that band; and control circuitry operable to generate the coarse and fine values so as to control the controllable oscillator. In certain arrangements, the control circuitry compensates for temperature fluctuations during operation.

A capacitor bank has a capacitance value that is discontinuous and has an extremely narrow variable range. Thus, in a case of obtaining a wide variable range of the capacitance value, a large number of capacitors are connected in parallel and used while being switched by switches. The present technology achieves at least one of: allowing the capacitance value of a variable capacitance circuit to be varied continuously by electrical control without increasing the parasitic capacitance; and decreasing the current consumption of an oscillator circuit using the variable capacitance circuit as compared to a conventional case. The variable capacitance circuit includes: a transconductance circuit that includes a MOS transistor; an inductor that is connected in parallel to the transconductance circuit; and a Gm control circuit that varies a transconductance of the MOS transistor.

Certain aspects of the present disclosure generally relate to techniques and apparatus for jitter detection using time-based and/or voltage-based techniques. An example jitter detection circuit generally includes: a comparator having a first input coupled to an input of the jitter detection circuit; a first combiner having an input coupled to an output of the comparator; an accumulator having an input coupled to an output of the first combiner, an output of the accumulator being coupled to an output of the jitter detection circuit; and a digital-to-analog converter (DAC) having an input coupled to the output of the accumulator, an output of the DAC being coupled to a second input of the comparator.

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.