A signal generation circuit comprises a VCO configured to generate a signal with a frequency corresponding to a control voltage; a divider configured to generate a divided signal by dividing the frequency of the signal generated by the VCO; a phase comparator configured to compare a reference clock signal generated by a reference oscillator and the divided signal generated by the divider; a charge pump configured to output a current corresponding to a comparison result of the phase comparator; a loop filter configured to generate a voltage corresponding to the current output by the charge pump; a switched capacitor filter configured to generate, by sampling the voltage generated by the loop filter, a control voltage of the VCO in a steady state; and an initial-value provision circuit configured to provide an initial value of the control voltage of the VCO.

A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data from the processor. The circuit device also includes at least one of a first register that stores phase comparison result data, a second register in which one of offset adjustment data for GPS and offset adjustment data for UTC is set, and a third register in which offset adjustment data for adjusting a phase difference is set.

A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

An oscillator circuit includes: an oscillator, oscillating a resonator and generating a first oscillation signal; and a PLL circuit, adjusting a ratio between a first frequency of the first oscillation signal and a second frequency of a second oscillation signal output from a voltage controlled oscillator, and controlling the oscillator based on a loop filter voltage being an input voltage of the voltage controlled oscillator.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

A first capacitor has a capacitance adjustable to a set point value by application of a bias voltage. A second capacitor also has a capacitance adjustable to a set point value by application of a bias voltage. The first and second capacitors are arranged to receive the same bias voltage generated by a control circuit. The control circuit receiving the set point value as an input and generates that bias voltage in response to a quantity representative of a capacitance of the second capacitor.

The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increased or decreased based upon a detected vibration level. In an embodiment, the phase locked loop includes a controllable oscillator, an output module, a filter module and a detector. The filter module can be configured to receive a bandwidth control signal to modify a bandwidth of the phase locked loop based on a vibration signal. In an embodiment, the vibration signal corresponds to a vibration level experienced by the phased locked loop. The detector can be configured to receive a PLL output signal from the output module and to receive a PLL input signal.

A clock generator includes a first phase-locked loop (PLL), a converter circuit, and a second PLL. The first PLL generates an oscillating signal based on a reference signal and outputs a noise signal indicating a noise component of the oscillating signal. The converter circuit produces an electrical signal based on the noise signal. The second PLL receives the electrical signal from the converter circuit at a loop filter of the second PLL and generates a clock signal based on the oscillating signal and the electrical signal.

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.