There is provided a phase locked loop circuit including a phase-frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on first phase difference, and generate a first and a second control signals based on the phase gain, a lock detection circuit configured to generate a lock detection signal based on the first phase difference, a charge pump circuit configured to generate a loop filter input signal based on the first and second control signals, a loop filter configured to adjust impedance based on the activated lock detection signal and generate a loop filter output signal based on the adjusted impedance, an oscillator configured to generate a clock signal based on the loop filter output signal, and a divider configured to generate the feedback clock signal by dividing the clock signal.

A phase-locked loop device and a method for operating the same, including: a voltage-controlled oscillator configured to generate an output clock signal; a divider configured to divide the output clock signal into a first phase division signal; a sampling phase frequency detector configured to: receive a first supply voltage, a second supply voltage different from the first supply voltage, and the first phase division signal, and based on determining that a phase difference between the first phase division signal and a reference clock signal corresponds to a first interval, output a hold voltage and a status signal for the phase difference; a transconductance circuit configured to output a first conversion current based on the hold voltage; a charge pump configured to output a second conversion current based on the status signal; and a loop filter configured to provide a voltage control signal to the voltage-controlled oscillator.