A framework for power management. The framework includes at least one power distribution board disposed within a radio-frequency (RF) cabin of a medical imaging system and coupled to an external reference clock. The power distribution board may include a clock circuit that generates one or more output clock signals based on a reference clock signal from the external reference clock. One or more switching regulators may be coupled to the clock circuit. The one or more switching regulators may be synchronized to the one or more output clock signals and provide power to one or more endpoint loads.

An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage. Furthermore, the circuit includes a control circuit that is configured to activate, dependent on a control signal, either the first switchable resistor network, the second switchable resistor network or both, the first and the second resistor networks.

A method and system of controlling a power converter coupled between a power generator and an electric grid. The method comprises detecting a grid disturbance voltage dip event while the power converter operates in a first phase locked loop (PLL) control mode that establishes a state of synchronization with the electric grid, the power converter electrically coupled to either motor drive inverter or grid-tie inverter, detecting a loss of the state of synchronization with the electric grid in conjunction with progressive charge depletion from a charged state of the dc-link capacitors, switching the converter to a diode mode of operation, switching from the first PLL control mode to a second PLL control mode of operation of the power converter, and re-establishing the state of synchronization to timely pre-empt progressive depletion of charge from the dc-link capacitors while under the second PLL control mode of operation of the power converter.

A method and system of controlling a power converter coupled between a power generator and an electric grid. The method comprises detecting a grid disturbance voltage dip event while the power converter operates in a first phase locked loop (PLL) control mode that establishes a state of synchronization with the electric grid, the power converter electrically coupled to either motor drive inverter or grid-tie inverter, detecting a loss of the state of synchronization with the electric grid in conjunction with progressive charge depletion from a charged state of the dc-link capacitors, switching the converter to a diode mode of operation, switching from the first PLL control mode to a second PLL control mode of operation of the power converter, and re-establishing the state of synchronization to timely pre-empt progressive depletion of charge from the dc-link capacitors while under the second PLL control mode of operation of the power converter.

A method includes generating first frequency metrics for a first received network clock signal using a local reference clock signal. The method includes, in response to the first received network clock signal being available and satisfying a quality metric, generating a network delay estimate using a first error estimate based on the first received network clock signal, and updating stored frequency metrics for the first received network clock signal with the first frequency metrics. The method includes generating an output clock signal based on received packets and the network delay estimate. The first frequency metrics for the first received network clock signal may include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage. Furthermore, the circuit includes a control circuit that is configured to activate, dependent on a control signal, either the first switchable resistor network, the second switchable resistor network or both, the first and the second resistor networks.

A digital clean-up oscillator and associated method are provided for cleaning jitter from a noisy clock signal, comprising receiving a reference clock oscillator signal and the noisy clock signal to be cleaned: measuring the frequency of the reference clock signal in the time domain of the noisy clock signal: filtering any frequency variations from the measured frequency of the reference clock signal on timescales shorter than a phase change interval Tau_clean over which jitter in the noisy clock signal is to be cleaned; generating a phase increment signal DDS_pinc based on the measured and filtered frequency of the reference clock signal: clocking the phase increment signal DDS_pinc with the reference clock signal for generating an output digital phase ramp signal ?_DDS(t) that tracks the frequency of the noisy clock signal with phase wander removed on timescales less than the phase change interval Tau_clean; and converting the output digital phase ramp signal ?_DDS(t) to an output jitter-cleaned time domain clock signal frequency locked to the noisy clock signal.

An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.