A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.