An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

In one embodiment, a device in a low-power and lossy network (LLN) makes, based on a temperature measurement, a first adjustment to a frequency for a wireless channel used by the device to communicate with one or more neighboring devices in the LLN. The device receives, via the wireless channel, a packet from one of the neighboring devices that indicates a transmit frequency for the packet. The device calculates a frequency offset based on a difference between the transmit frequency for the packet and the adjusted frequency for the wireless channel. The device makes, based on the calculated frequency offset, a second adjustment to the frequency for the wireless channel used by the device to communicate with the one or more neighboring devices in the LLN.

A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.

In one embodiment, a device in a low-power and lossy network (LLN) makes, based on a temperature measurement, a first adjustment to a frequency for a wireless channel used by the device to communicate with one or more neighboring devices in the LLN. The device receives, via the wireless channel, a packet from one of the neighboring devices that indicates a transmit frequency for the packet. The device calculates a frequency offset based on a difference between the transmit frequency for the packet and the adjusted frequency for the wireless channel. The device makes, based on the calculated frequency offset, a second adjustment to the frequency for the wireless channel used by the device to communicate with the one or more neighboring devices in the LLN.

A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.

A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.