In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

A frequency locked loop is disclosed. The disclosed frequency locked loop may include: a voltage-controlled oscillator configured to output a LO signal; a mixer configured to mix an RF signal with the LO signal to output an IF signal; a first IF path part configured to transfer the IF signal; a second IF path part configured to transfer the IF signal; and an error amplifier configured to receive output signals of the first IF path part and output signals of the second IF part as input, where the voltage-controlled oscillator adjusts a frequency of the LO signal based on an output signal of the error amplifier, the first IF path part has the conversion gain decreased according to an increase in the frequency of the IF signal, and the second IF path part has the conversion gain increased according to an increase in the frequency of the IF signal.

A frequency locked loop is disclosed. The disclosed frequency locked loop may include: a voltage-controlled oscillator configured to output a LO signal; a mixer configured to mix an RF signal with the LO signal to output an IF signal; a first IF path part configured to transfer the IF signal; a second IF path part configured to transfer the IF signal; and an error amplifier configured to receive output signals of the first IF path part and output signals of the second IF part as input, where the voltage-controlled oscillator adjusts a frequency of the LO signal based on an output signal of the error amplifier, the first IF path part has the conversion gain decreased according to an increase in the frequency of the IF signal, and the second IF path part has the conversion gain increased according to an increase in the frequency of the IF signal.

The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.