A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.

A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.

A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.

A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.

A controller for use in a power converter including a jitter generator circuit coupled to receive a drive signal from a switch controller and generate a jitter signal. The jitter signal is a modulated jitter signal when the drive signal is below a first threshold frequency. The switch controller is coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a current through the power switch. The switch controller is coupled to generate the drive signal to control switching of the power switch in response to the current sense signal and the jitter signal to control a transfer of energy from an input of the power converter to an output of the power converter.

A controller for use in a power converter includes a jitter generator circuit coupled to receive a drive signal from a switch controller and generate a jitter signal. The switch controller is coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a drain current through the power switch. The switch controller is coupled to generate the drive signal to control switching of the power switch in response to the current sense signal and the jitter signal to control a transfer of energy from an input of the power converter to an output of the power converter.

A controller for use in a power converter includes a jitter generator circuit coupled to receive a drive signal from a switch controller and generate a jitter signal. The switch controller is coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a drain current through the power switch. The switch controller is coupled to generate the drive signal to control switching of the power switch in response to the current sense signal and the jitter signal to control a transfer of energy from an input of the power converter to an output of the power converter.

A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.