A controller for use in a power converter including a jitter generator circuit coupled to receive a drive signal from a switch controller and generate a jitter signal. The jitter signal is a modulated jitter signal when the drive signal is below a first threshold frequency. The switch controller is coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a current through the power switch. The switch controller is coupled to generate the drive signal to control switching of the power switch in response to the current sense signal and the jitter signal to control a transfer of energy from an input of the power converter to an output of the power converter.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip. The phase locked loop-based power supply circuit includes: a phase locked loop circuit, including a voltage-controlled oscillator (VCO), the phase locked loop circuit outputs, through an output end of the phase locked loop circuit, a control voltage for controlling the VCO; and a voltage regulator, an input end of the voltage regulator is connected with the output end of the phase locked loop circuit, to make the control voltage outputted by the phase locked loop circuit form a power supply voltage after passing through the voltage regulator; the power supply voltage is used for supplying power for a load circuit; the load circuit includes at least one logic gate. The phase locked loop-based power supply circuit reduces timing variations in a digital circuit, and is conducive to implementing timing closure.

The present disclosure provides a phase locked loop-based power supply circuit and method, and a chip. The phase locked loop-based power supply circuit includes: a phase locked loop circuit, including a voltage-controlled oscillator (VCO), the phase locked loop circuit outputs, through an output end of the phase locked loop circuit, a control voltage for controlling the VCO; and a voltage regulator, an input end of the voltage regulator is connected with the output end of the phase locked loop circuit, to make the control voltage outputted by the phase locked loop circuit form a power supply voltage after passing through the voltage regulator; the power supply voltage is used for supplying power for a load circuit; the load circuit includes at least one logic gate. The phase locked loop-based power supply circuit reduces timing variations in a digital circuit, and is conducive to implementing timing closure.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.