A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.

A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.

A method and apparatus for generating a digital signal indicating a time between a start and a stop signal, including a short inverter ring operable to generate a clock signal. The clock signal is provided to a time-interleaved counter array that distributes the clock signal on a plurality of clock outputs as interleaved clock signals. Each interleaved clock signal is provided to a counter that counts a partial count value. The partial count values are combined to obtain a total count value as the digital signal indicating the time. A fine resolution signal is obtained from a chain of stochastic flip flops connected to outputs of the inverters in the short inverter ring. Multiple clock signal outputs of the inverter ring may be provided to multiple interleaved counters.

A method and apparatus for generating a digital signal indicating a time between a start and a stop signal, including a short inverter ring operable to generate a clock signal. The clock signal is provided to a time-interleaved counter array that distributes the clock signal on a plurality of clock outputs as interleaved clock signals. Each interleaved clock signal is provided to a counter that counts a partial count value. The partial count values are combined to obtain a total count value as the digital signal indicating the time. A fine resolution signal is obtained from a chain of stochastic flip flops connected to outputs of the inverters in the short inverter ring. Multiple clock signal outputs of the inverter ring may be provided to multiple interleaved counters.

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.

A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.

A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.

A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.