There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.

A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.

A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.