A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

This application relates to a device and a method for eliminating electromagnetic interference (EMI). The device for eliminating EMI includes: a timing control chip; and a phase-locked loop module, electrically connected to the timing control chip and including: a phase detection unit, configured to detect a frequency generated by a clock cycle to generate a frequency difference; a charge pump unit, configured to generate a regulation voltage; a voltage-controlled oscillator unit, configured to control an oscillation frequency when the regulation voltage is input; a plurality of frequency divider units, configured to generate a new output clock frequency by using an input clock frequency; and a selector unit, configured to select the appropriate frequency divider units, where the selector unit has another end electrically connected to needed power circuits.

A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

A first 1:N frequency divider has an input configured to be coupled to one of two signals and a second 1:N frequency divider has an input configured to be coupled to another of the two signals. A mixer includes two inputs, where each input is coupled to an output of one of the first and second 1:N frequency dividers. A low-pass filter has an input coupled to an output of the mixer and an analog-to-digital converter (ADC) has an input coupled to an output of the low-pass filter. A data collection and analysis block repeatedly changes a phase of an output of the first 1:N divider, collects a set of digitized data generated by the ADC, and estimates the phase difference between the two signals based on the set of digitized data.

A first 1:N frequency divider has an input configured to be coupled to one of two signals and a second 1:N frequency divider has an input configured to be coupled to another of the two signals. A mixer includes two inputs, where each input is coupled to an output of one of the first and second 1:N frequency dividers. A low-pass filter has an input coupled to an output of the mixer and an analog-to-digital converter (ADC) has an input coupled to an output of the low-pass filter. A data collection and analysis block repeatedly changes a phase of an output of the first 1:N divider, collects a set of digitized data generated by the ADC, and estimates the phase difference between the two signals based on the set of digitized data.

A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.

A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.