An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.

A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.

A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).

A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.

Apparatus and methods are disclosed that utilize magnetically differential loop filter capacitor elements that are physically positioned adjacent voltage-controlled oscillator (VCO) inductor/s in the device layout of a phase locked loop (PLL) circuit. Such a PLL circuit may be employed, for example, to produce a PLL output signal for RF receivers, RF transmitters, RF transceivers and any other type of circuit configured to utilize a PLL output signal having a phase that is based on the phase of an input signal.