A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.

A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator (2) operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider (14) connected to said first output (12) and providing a second output at a second frequency; and a phase detector (4) controlling said voltage controlled oscillator (2) on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output (10, 12) provides said target frequency output signal.

An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

The present disclosure discloses a wireless radio-frequency transmission apparatus, comprising: a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator, wherein the twin voltage-controlled oscillator comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator which are of the same structure, wherein when the twin voltage-controlled oscillator is in a reception mode, the first voltage-controlled oscillator and the second voltage-controlled oscillator are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers for receiving information; and when the twin voltage-controlled oscillator is in a transmission mode, the first voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second voltage-controlled oscillator is used for performing frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.

Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.