Aspects described herein include devices and methods for phase lock loop (PLL) output sharing between multiple communication chains in a wireless communication apparatus. In one aspect, an apparatus includes phase locked loop (PLL) circuitry having a shared PLL output, radar signal generation circuitry, a first transmission chain coupled to the shared PLL output and the radar signal generation circuitry, and a second transmission chain coupled to the shared PLL output and the radar signal generation circuitry.

Aspects described herein include devices and methods for phase lock loop (PLL) output sharing between multiple communication chains in a wireless communication apparatus. In one aspect, an apparatus includes phase locked loop (PLL) circuitry having a shared PLL output, radar signal generation circuitry, a first transmission chain coupled to the shared PLL output and the radar signal generation circuitry, and a second transmission chain coupled to the shared PLL output and the radar signal generation circuitry.

Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.

Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.

Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.

Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.

A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.

Systems and methods for synchronizing networks are described. A phase monitor circuit can determine at least one phase offset among a plurality of reference clock signals. A timing circuit can generate an output clock signal using a primary reference clock. The primary reference clock can be among the plurality of reference clock signals. The timing circuit can determine failure of the primary reference clock. The timing circuit can, in response to the failure of the primary reference clock, generate the output clock signal using a specific phase offset and a secondary reference clock for the PLL. The specific phase offset can be among the at least one phase offset determined by the phase monitor circuit, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock can be among the plurality of reference clock signals.

Systems and methods for synchronizing networks are described. A phase monitor circuit can determine at least one phase offset among a plurality of reference clock signals. A timing circuit can generate an output clock signal using a primary reference clock. The primary reference clock can be among the plurality of reference clock signals. The timing circuit can determine failure of the primary reference clock. The timing circuit can, in response to the failure of the primary reference clock, generate the output clock signal using a specific phase offset and a secondary reference clock for the PLL. The specific phase offset can be among the at least one phase offset determined by the phase monitor circuit, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock can be among the plurality of reference clock signals.

Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.