A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal.

A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.