A method for setting a system clock of an integrated circuit. The integrated circuit has an oscillator module which specifies a system clock of the integrated circuit, a counter module, a signal input, and a communication interface. The method includes: receiving a reference signal at the signal input for a predefined duration; incrementing the counter module by one per system clock of the integrated circuit over the duration of the application of the reference signal; ascertaining a counter value of the counter module after expiration of the duration; receiving a counter target value at the communication interface, which counter target value corresponds to a number of system clocks at a target frequency during the duration; comparing the counter value of the counter module with the counter target value and correcting a frequency of the oscillator module based on a deviation of the counter value from the counter target value.

A method for setting a system clock of an integrated circuit. The integrated circuit has an oscillator module which specifies a system clock of the integrated circuit, a counter module, a signal input, and a communication interface. The method includes: receiving a reference signal at the signal input for a predefined duration; incrementing the counter module by one per system clock of the integrated circuit over the duration of the application of the reference signal; ascertaining a counter value of the counter module after expiration of the duration; receiving a counter target value at the communication interface, which counter target value corresponds to a number of system clocks at a target frequency during the duration; comparing the counter value of the counter module with the counter target value and correcting a frequency of the oscillator module based on a deviation of the counter value from the counter target value.

Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

The present disclosure provides a circuit, which includes a clock generator, a selection control circuit, and a selection circuit. The clock generator is configured to divide an input clock signal into a first divided clock set and a second divided clock set, and generate a control clock set from the first divided clock set and the second divided clock. The selection control circuit is configured to generate a first selection signal and a second selection signal using the control clock set. The selection circuit is configured to sequentially output each bit of an input data signal within a duration of predetermined clock cycles of the input clock signal based on the first selection signal and the second selection signal.

The present disclosure provides a circuit, which includes a clock generator, a selection control circuit, and a selection circuit. The clock generator is configured to divide an input clock signal into a first divided clock set and a second divided clock set, and generate a control clock set from the first divided clock set and the second divided clock. The selection control circuit is configured to generate a first selection signal and a second selection signal using the control clock set. The selection circuit is configured to sequentially output each bit of an input data signal within a duration of predetermined clock cycles of the input clock signal based on the first selection signal and the second selection signal.

The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.

The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.

A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers includes synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases including a common phase. The global reset is applied to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase.

A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers includes synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases including a common phase. The global reset is applied to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase.