Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.

Pulsed hyperspectral imaging without input clock or data transmission clock is disclosed. A system includes an emitter for emitting pulses of electromagnetic radiation and an image sensor comprising a pixel array for sensing reflected electromagnetic radiation. The system includes a plurality of bidirectional data pads and a controller in communication with the image sensor. The system is such that at least a portion of the pulses of electromagnetic radiation emitted by the emitter comprises one or more of: electromagnetic radiation having a wavelength from about 513 nm to about 545 nm; electromagnetic radiation having a wavelength from about 565 nm to about 585 nm; or electromagnetic radiation having a wavelength from about 900 nm to about 1000 nm.

Pulsed fluorescence imaging without input clock or data transmission clock is disclosed. A system includes an emitter for emitting pulses of electromagnetic radiation and an image sensor comprising a pixel array for sensing reflected electromagnetic radiation. The system includes a plurality of bidirectional data pads and a controller in communication with the image sensor. The system is such that at least a portion of the pulses of electromagnetic radiation emitted by the emitter comprises one or more of: electromagnetic radiation having a wavelength from about 770 nm to about 790 nm; or electromagnetic radiation having a wavelength from about 795 nm to about 815 nm.

Pulsed laser mapping imaging without input clock or data transmission clock is disclosed. A system includes an emitter for emitting pulses of electromagnetic radiation and an image sensor comprising a pixel array for sensing reflected electromagnetic radiation. The system includes a plurality of bidirectional data pads and a controller in communication with the image sensor. The system is such that at least a portion of the pulses of electromagnetic radiation emitted by the emitter comprises a laser mapping pattern.

Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.