Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

An apparatus includes a coarse resolver configured to output coarse position signals indicative of a coarse position of a drive shaft of a motor. The apparatus also includes a fine resolver configured to output fine position signals indicative of a fine position of the drive shaft of the motor. The apparatus further includes a control circuit. The control circuit is configured to receive the coarse position signals from the coarse resolver and the fine position signals from the fine resolver and generate an initial position output, based on the coarse position signals, that indicates an initial position of the drive shaft. The control circuit is further configured to generate a subsequent position output, based on the fine position signals, that indicates a subsequent position of the drive shaft.

Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

Devices and methods for digital to analog conversion (DAC) are provided, in which the analog outputs of an even number of digital to analog converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analog outputs are subtracted. Dither and filtering techniques may also be employed.

Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed.

A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

A self-adaptive SAR ADC techniques that can increase speed and/or decrease its power consumption. In some example approaches, one or more bits from a conversion of a previous sample of an analog input signal can be preloaded onto a DAC circuit of the ADC. If the preloaded bits are determined to be acceptable, bit trials on the current sample can be performed to determine the remaining bits. If not acceptable, the ADC can discard the preloaded bits and perform bit trials on all of the bits. The self-adaptive SAR ADC can include a control loop to adjust, e.g., increase or decrease, the number of bits that are preloaded in a subsequent bit trial using historical data.

Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.