The invention relates to a method for processing high speed analogue signals in real time, characterized in that it comprises the following steps: a) high speed analogue signals are provided to the microprocessor (1), b) using a high speed ADC converter (2) integrated in said microprocessor (1), these signals are quantized and converted to digital form without further processing, c) the digital data thus acquired is sent via an interface (3), in particular a high speed interface, and an input data busbar (4), to a high speed signal processing unit (5), d) said digital data is processed in the high speed signal processing unit (5) in line with the processing feature (6) implemented in said unit (5), e) the processing result is sent via an interface (7), in particular a high speed interface, and an output data busbar (8), to the microprocessor (1), f) the microprocessor (1) is used to perform operations on the processed data received in line with the program (9) implemented in this microprocessor (1).

The invention also relates to a system for application of this method.

The current disclosure is related to a column and line digital-to-analog converter (DAC) with a hybrid coupler for generating quadrature analog signals. The DAC may include an array of unit power amplifiers (cells). A first portion of the cells of the array may be coupled to a first column decoder to receive in-phase components of digital signals and a second portion of the cells may be coupled to a second column decoder to receive quadrature components of the digital signals. The first portion of the cells of the array may generate in-phase components of analog signals and the second portion of the cells of the array may generate quadrature components of the analog signals. A hybrid coupler of the DAC may receive the in-phase and quadrature components of the analog signals with a similar phase, delay the quadrature components by a phase delay (e.g., 90 degrees), and output the resulting analog signals.

A method of optimizing a quantization step size of an analog-to-digital converter (ADC) based on a number of crossbar arrays of a computing device includes: generating a first mapping relationship between the quantization step size of the ADC and a first root mean square error, the first root mean square error reflecting a quantization error and a clipping error, wherein the generating the first graph is based on use of only a single crossbar array; generating a second mapping relationship between the quantization step size of the ADC and a second root mean square error, the second root mean square error reflecting a quantization error, wherein the generating the second mapping is based on a uniform distribution of a total sum of quantization errors; and determining the quantization step size of the ADC based on the first mapping relationship and the second mapping relationship.

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0kM, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.

Disclosed is a method that includes generating a prediction consistency value that indicates a consistency of prediction of an object in an input image with respect to class prediction values for the object in an input image from classification models to which the input image is input, and identifying a class of the object. Identifying the class of the object includes, in response to a class type being determined, based on the prediction consistency value, of the object being determined to correspond to a majority class, identifying a class of the object based on a corresponding class prediction value output for the object from a majority class prediction model, and in response to the class type of the object being determined to correspond to a minority class, identifying the class of the object based on another corresponding class prediction value output for the object from a minority class prediction model.

The current disclosure is related to a column and line digital-to-analog converter (DAC) with a hybrid coupler for generating quadrature analog signals. The DAC may include an array of unit power amplifiers (cells). A first portion of the cells of the array may be coupled to a first column decoder to receive in-phase components of digital signals and a second portion of the cells may be coupled to a second column decoder to receive quadrature components of the digital signals. The first portion of the cells of the array may generate in-phase components of analog signals and the second portion of the cells of the array may generate quadrature components of the analog signals. A hybrid coupler of the DAC may receive the in-phase and quadrature components of the analog signals with a similar phase, delay the quadrature components by a phase delay (e.g., 90 degrees), and output the resulting analog signals.

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0kM, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the the first voltage equals the second voltage.