Examples disclosed herein relate to averaging modules. For example, a method may include obtaining, by an analog-to-digital converter (ADC), a plurality of samples of an input analog signal. The method may also include determining, by an averaging module, a sum value of the plurality of samples, such that a set of most significant bits of the sum value represent an average value of the plurality of samples. The method may further include determining the average value based at least on the set of most significant bits, and outputting the average value to a bus coupled to a memory module.

It is described an electronic device (1) for measuring an electric quantity, comprising: an analog-digital conversion module (2) configured to digitally convert time portions of an analog signal (S.sub.M(t)) to be measured alternated with time portions of a reference analog signal (S.sub.R(t)), for supplying respective first (D.sub.SM) and second pluralities (D.sub.R) of digital values and a digital processing module (3) configured to: calculate a first mean amplitude (A1) of the first pluralities of digital values, and a second mean amplitude (A2) of the second pluralities of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module (2); supply a ratio value (V.sub.RT) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (S.sub.M(t)) to be measured.

A successive approximation Analog to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analog converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analog converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analog conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than what can be represented by the least significant bit of the digital output of the SAR. In normal operation, successive outputs of a SAR for the same input will result in the same digital value output and the same residual. By storing the residual at the end of each conversion and adding the residual onto the input signal of the next conversion the residuals are accumulated over time so that they may affect the output digital value. After a number of conversions, the accumulated residuals add up to more than the value represented by the LSB of the register and the digital value will be one higher than if a conversion had been performed on the input signal alone. In this way, the residual signal affects the output value in time and thus can be taken into account by processing the digital output in the time domain.

Examples disclosed herein relate to averaging modules. For example, a method may include obtaining, by an analog-to-digital converter (ADC), a plurality of samples of an input analog signal. The method may also include determining, by an averaging module, a sum value of the plurality of samples, such that a set of most significant bits of the sum value represent an average value of the plurality of samples. The method may further include determining the average value based at least on the set of most significant bits, and outputting the average value to a bus coupled to a memory module.

Provided are apparatuses and methods, in which a disturbed measurement variable is converted to a digital signal. The digital signal is then averaged over a number of sampling values which corresponds to a period of the disturbances.

An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.

An image capturing apparatus is provided. The apparatus comprises a pixel array, a signal generator that generates a comparison signal whose electric potential changes with time and a converter that converts a pixel signal into a digital signal. The comparison signal starts to change from a first electric potential in accordance with a start of the conversion of the pixel signal by the converter, and changes again, in accordance with inversion of a magnitude relationship between the pixel signal and the comparison signal, from a third electric potential between the first electric potential and a second electric potential at which the magnitude relationship is inverted. The converter includes a counter that holds, as a signal value, a count value obtained by counting from the start of the conversion of the pixel signal until the inversion of the magnitude relationship.

Image sensors using multiple-ramp single slope analog to digital converters (ADCs) and method of their operation are disclosed. The images sensors use additional column ADCs to detect offset errors in the fine ramp signals and feedback in the analog domain to correct the errors. Averaging errors over multiple analog-to-digital conversion cycles allows for improved error correction.

An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (nm)-bit RDAC to provide an intermediate voltage responsive to the nm least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

A measurement unit is disclosed and includes a converter unit and a processing unit is configured to provide a measurement result value, based on a first input signal and a second input signal. The converter unit is configured to provide a first digital, quantized values based on the first input signal or derived from the first input signal and the second input signal. The converter unit is further configured to provide second digital, quantized values based on the second input signal. The measurement unit is configured to change the one or more control signals of the converter unit between determination of different first values or a determination of the different second values, wherein different first values and/or different second values are provided using different converter quantization step sizes.