Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

A digital-to-analog converter having a structure that converter may decrease an effect of a mismatch between elements and decrease a quantity of the elements. The digital-to-analog converter includes a multiplexer configured to output a first voltage or a second voltage corresponding to an input bit as an input voltage and a recursive switched circuit configured to alternately receive the input voltage and a reference voltage and to output an average value of the input voltage and the reference voltage as an output voltage.

An A/D converter includes: an input unit configured to receive an analog input signal, a preprocessing unit configured to convert the input signal into a digital preprocessing signal based on a dynamic range of the input signal and a first resolution corresponding to a predetermined first bit number, a first conversion unit configured to convert the preprocessing signal into a first output signal based on a second resolution corresponding to a second bit number smaller than the first bit number, and a second conversion unit configured to convert the preprocessing signal into a second output signal based on a third resolution corresponding to a third bit number which is smaller than the first bit number and is different from the second bit number.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partiallye.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

An A/D converter includes: an input unit configured to receive an analog input signal, a preprocessing unit configured to convert the input signal into a digital preprocessing signal based on a dynamic range of the input signal and a first resolution corresponding to a predetermined first bit number, a first conversion unit configured to convert the preprocessing signal into a first output signal based on a second resolution corresponding to a second bit number smaller than the first bit number, and a second conversion unit configured to convert the preprocessing signal into a second output signal based on a third resolution corresponding to a third bit number which is smaller than the first bit number and is different from the second bit number.

A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

A circuit for digital-to-analog conversion includes a first digital-to-analog converter (DAC), a second DAC, and an output node. The first DAC provides charges from multiple first charge sources segmented into a first group for most significant bits of a digital input to the first DAC and a second group for least significant bits of the digital input. Dither is both added to the digital input to the first DAC and used as sole digital input to the second DAC. Analog output from the second DAC is subtracted from analog output of the first DAC at the output node so as to cancel the dither added to the first DAC.

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

A data converter includes multiple subunits to convert an input such as a radio frequency (RF) signal. The subunits are selected to sample the input in an order that varies over time. Two or more subunits are enabled at the same time. The selected subunits are configured to convert the input from an analog signal to a digital signal or vice versa.