A system and method of analog to digital conversion including an adjustable ADC, FIR filter circuitry, and a noise setting controller. The ADC samples an analog input signal to provide digital samples at a sample rate that is Y times an output rate of output digital values. The FIR filter circuitry includes Y taps with Y corresponding coefficients and is configured to filter the digital samples from the ADC and to provide filtered digital samples at the sample rate. decimation circuitry may be included to decimate the filtered digital samples by Y to provide the output digital values. The noise setting controller provides an adjustment value to the ADC to adjust noise contribution of the digital samples provided by the ADC based on corresponding coefficients of the FIR filter circuitry. The ADC is adjusted to reduce noise contribution of digital samples that correspond with higher FIR filter coefficients.

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C.sub.n[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V.sub.d and the digital output port.

A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C.sub.n[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V.sub.d and the digital output port.

Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

According to one embodiment, an A/D converter includes a successive approximation algorithm setting register that stores a plurality of successive approximation algorithms, an algorithm selection unit that selects a predetermined successive approximation algorithm from the plurality of successive approximation algorithms, a control circuit that generates a comparison value based on the selected predetermined successive approximation algorithm, a DAC that generates a comparison voltage from the comparison value, and a comparator that compares an analog input voltage with the comparison voltage. The control circuit generates a comparison value from a result of the comparison made by the comparator based on the selected predetermined successive approximation algorithm, and converts an analog input voltage into a digital signal from the result of the comparison made by the comparator the number of times equal to the number of bits of the digital signal.