Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.

The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

A device includes a first conversion stage, a second conversion stage, and a first filter circuit. The first conversion stage is configured to perform a Delta-Sigma modulation based on an input signal, in order to generate a first quantized signal and a first residual signal. The second conversion stage is configured to perform a pipelined successive approximation algorithm in response to the first residual signal, in order to generate a second quantized signal. The first filter circuit is configured to perform a decimation process based on the first quantized signal and the second quantized signal to generate a digital output signal.

Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

Techniques are provided for implementing a file system format for persistent memory. A node, comprising persistent memory, receives an operation comprising a file identifier and file system instance information. A list of file system info objects are evaluated to identify a file system info object matching the file system instance information. An inofile, identified by the file system info object as being associated with inodes of files within an instance of the file system targeted by the operation, is traversed to identify an inode matching the file identifier. If the inode comprises an indicator that the file is tiered into the persistent memory, then the inode it utilized to facilitate execution of the operation upon the persistent memory. Otherwise, the operation is routed to a storage file system tier for execution by a storage file system upon storage associated with the node.

A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.