A pulse signal compensation circuit of a pulse generator can include a pulse measurement circuit and a compensation generator circuit. The pulse measurement circuit can be configured to receive a plurality of pulse signals and to generate an average duty cycle or pulse overlap signal proportional to the duty cycle or pulse overlap of the plurality of pulses. The compensation generator circuit can be configured to receive the average duty cycle or pulse overlap signal and generate a duty cycle or pulse overlap compensation signal based on the average duty cycle or pulse overlap signal. The compensation signal can be utilized to adjust the duty cycle, amount of positive or negative pulse width overlap, and or the like of the plurality of pulse signals.

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to convert an analog signal to a digital signal in electronic devices and other applications that perform digital signal processing on the signal. The methods/systems can greatly reduce the nominal sampling rate for such applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/f.sub.s. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of f.sub.s/R, and drives an analog output responsive to each second digital input for a duration of RT. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of f.sub.s.

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

A method for encoding multiple audio signals comprises random sampling and quantizing each of the multiple audio signals, and encoding the sampled and quantized multiple audio signals as side information that can be used for decoding and separating the multiple audio signals from a mixture of said multiple audio signals. A method for decoding a mixture of multiple audio signals comprises decoding and demultiplexing side information, the side information comprising quantized samples of each of the multiple audio signals, receiving or retrieving from any data source a mixture of said multiple audio signals, and generating multiple estimated audio signals that approximate said multiple audio signals, wherein said quantized samples of each of the multiple audio signals are used.

A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub-analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between the plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably.