Patent classifications
H03M1/165
Metastability error detection and BER improvement technique in pipelined ADCs
In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
METASTABILITY ERROR DETECTION AND BER IMPROVEMENT TECHNIQUE IN PIPELINED ADCS
In an example, a system includes a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path. The main path includes a first stage having a sampling switch, a flash ADC having an input coupled to the sampling switch, a digital-to-analog converter (DAC) having an input coupled to an output of the flash ADC, and a first amplifier having an input coupled to an output of the DAC and the sampling switch. The main path includes a second stage coupled to the first stage and an input of a second amplifier. The main path also includes a backend ADC having an input coupled to an output of the second amplifier. The auxiliary path includes a plurality of metastability comparators coupled to the flash ADC.
Electronic apparatus
An electronic apparatus includes: a processor; a first electronic circuit that outputs a pulse width modulation signal; a low-pass filter circuit that outputs a voltage based on the pulse width modulation signal; a second electronic circuit that outputs an analog signal by using the output voltage of the low-pass filter circuit; and a third electronic circuit that converts the analog signal into a digital signal, and the processor sets a frequency of the pulse width modulation signal to a frequency at which a noise component included in the digital signal is reduced in relation to a sampling frequency of the third electronic circuit.