The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

An analog-to-digital converter ADC includes a first successive approximation register analog-to-digital converter (SAR ADC) configured to convert an in-phase input signal to digital data using a first integrator, a second successive approximation register analog-to-digital converter (SAR ADC) configured to convert a quadrature input signal to digital data using a second integrator, and first to fourth sampling capacitors configured to transmit an output of the first integrator to an input terminal of the second integrator, and transmit an output of the second integrator to an input terminal of the first integrator when the first integrator and the second integrator integrate the sampled in-phase input signal and the quadrature input signal, respectively. The first and second SAR ADCs and the first to fourth sampling capacitors are driven according to an operation sequence of a sampling stage, a conversion stage, and an integration stage.

An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Motion detection device consisting of a single encoder and a single stationary sensor element, the encoder, which is arranged on a movable part, representing an asymmetrical pattern. The angular velocity or velocity and the direction of motion of a moving part are determined from the sensor signal by measuring the edge steepness or the rise time or fall time, spectrally analyzing the frequency and the phase relation of a harmonic to the phase of the fundamental mode, or evaluating the asymmetries of a sequence of rectangular pulses.

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CT achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

A circuit comprising (1) one or more input devices configured to sense analog inputs, (2) at least one analog-to-digital converter communicatively coupled to the input devices and configured to convert the analog inputs into digital inputs, (3) at least one filter component communicatively coupled to the analog-to-digital converter and configured to output digital feedback based at least in part on the digital inputs, and (4) a digital-to-analog converter communicatively coupled to the filter component and configured to (A) convert the digital feedback into analog feedback and (B) output the analog feedback to facilitate removing the analog feedback from the analog inputs. Various other apparatus, systems, and methods are also disclosed.