A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

A method is described that is performed by a calibration system. The method includes determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system; generating a set of digital test values for determining the accuracy of the analog-to-digital converter; and applying the set of perturbation values to the set of digital test values to generate a set of modified test values, wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain.

A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.

A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.

An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator.

Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C.sub.n[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator V.sub.d and the digital output port.

A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.